FIG. 1 shows a cross sectional view of a pixel (110) used as part of a conventional four transistor (4T) pixel architecture (100). The pixel (110) comprises a P-type conducting region (140) formed in an N-type substrate (120). A pinning n+ layer (130) is also shown in FIG. 1. A combination of the pinning layer (130), the conducting region (140) and the substrate (120) forms a conventional pinned photodiode (135), as shown by a dotted line in FIG. 1.
A shallow trench isolation region (150) (STI) is further shown in FIG. 1. The STI region (150) isolates one pixel from another. The pixel (110) comprises also a transfer gate (160) provided on top of an insulating region (170).
In operation, during an integration period when the pixel (110) is exposed to light, the transfer gate (160) is OFF and charges (in this case holes) generated within the photodiode (135) are accumulated in the conducting region (140). After the integration period, the transfer gate (160) is turned on and the charges held in the conducting region (140) are transferred to a floating node (180). The floating node (180) is electrically connected to a 3T structure (125). After charges are transferred to the floating node (180), the transfer gate (160) is turned off again and a subsequent integration period will start.
The 3T structure (125) comprises a source follower (122), a reset transistor RST (121) and a row select transistor (123). The source follower (122) converts charge to output voltage. The reset transistor (121) resets the photodiode (135) before charge is integrated and the row select transistor (123) selects a row or line for readout.
The pixel (110) as described above is an example of conventional CMOS imagers with pinned photodiodes. Such devices when implemented in deep sub-micron technology, suffer from both reduced charge handling capacity and increased electrical cross-talk due to operation from a reduced power supply. The reduced voltage operation limits the maximum internal field and hence reduced depletion width. Both of these are responsible for increased cross-talk and limited charge handling capacity. For small pixels, lateral depletion cannot be extended due to the structure of the imager and therefore more lateral carrier diffusion due to thermal gradients, will result. The problem is more accentuated for a back-illuminated CMOS imager where the photo-generated carriers have to travel across the entire thickness of the device. In this case, there is a higher likelihood that the charges generated within the imager diffuse laterally and this results in a worse inter-pixel cross-talk.